As I wrote earlier, I have some problems to get my 65SC22 based SPI implementation to work, the SCLK signal is out-of-sync????
Luckily there might be another solution, the 65SPI/B implementation by André Fachat, which in turn is based in the 65SPI by Daryl Rictor. They both used Xilinx based CPLDs, which I don’t have lying around. (Also I lack a programmer for this IC family).
I did have an Altera EPM7064 lying around, so I set myself to rewrite the VHDL by André for the EPM7064. Luckily this seemed to work quite good, I didn’t have to rewrite much. I just programmed the EPM7064 a few days ago, which went without much trouble. You can download the project here: 65SPI/B for Altera.
Tonight I might get into some additional coding/testing of this idea…