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You can find the source of the GALs here. Previous versions will be available in 7zip files at the bottom of the page
U1 – GAL22v10 Chip Selects
;PALASM Design Description
;---------------------------------- Declaration Segment ------------
TITLE Lilith Memory Decoder MMU U1
PATTERN
REVISION 1.0.1
AUTHOR X. Maas
COMPANY
DATE 05/08/20
;
; 07-05-20 - v1.0 - Initial version
; 08-05-20 - v1.0.1 - Discovered that both RAM_CS and ROM_CS were
; asserted at the same time
;
CHIP _MMU_U1 PAL22V10
;---------------------------------- PIN Declarations ---------------
PIN 1 ADDR_VALID ;-- Active Low
PIN 2 BANK00 ;-- Active Low
PIN 3 A4 ;
PIN 4 A5 ;
PIN 5 A6 ;
PIN 6 A7 ;
PIN 7 A8 ;
PIN 8 A9 ;
PIN 9 A10 ;
PIN 10 A11 ;
PIN 11 A12 ;
PIN 23 BANKFF ;-- Active Low
PIN 22 ROM_HIGH ;-- Active Low
PIN 21 RAM_CS ;-- Active Low
PIN 20 ROM_CS ;-- Active Low
PIN 19 VIA_CS ;-- Active Low
PIN 18 ACIA_CS ;-- Active Low
PIN 17 CS_SLOT2 ;-- Active Low
PIN 16 CS_SLOT4 ;-- Active Low
PIN 15 A13 ;
PIN 14 A14 ;
PIN 13 A15 ;
;----------------------------------- Boolean Equation Segment ------
EQUATIONS
;
; ROM will be enabled when:
; Bank $00: $00E000-$00FFFF
; Bank $06 - $0C: $06/0000-$0C/FFFF
ROM_CS = /(/ADDR_VALID * (/ROM_HIGH + (A15 * A14 * A13 * /BANK00)) * VIA_CS * ACIA_CS * CS_SLOT2 * CS_SLOT4);
RAM_CS = /(/ADDR_VALID * ROM_CS * VIA_CS * ACIA_CS * CS_SLOT2 * CS_SLOT4);
;
; ACIA is located at $00DF00
ACIA_CS = /(/BANK00 * A15 * A14 * /A13 * A12 * A11 * A10 * A9 * A8 * /A7 * /A6 * /A5);
; VIA (e.g. LCD) is located at $DF20
VIA_CS = /(/BANK00 * A15 * A14 * /A13 * A12 * A11 * A10 * A9 * A8 * /A7 * /A6 * A5);
; CS_CLOT2 is located at $DF40
CS_SLOT2 = /(/BANK00 * A15 * A14 * /A13 * A12 * A11 * A10 * A9 * A8 * /A7 * A6 * /A5);
; CS_SLOT4 is located st $DF60
CS_SLOT4 = /(/BANK00 * A15 * A14 * /A13 * A12 * A11 * A10 * A9 * A8 * /A7 * A6 * A5);
;-------------------------------------------------------------------
U2 – GAL22v10 Bank Decoder
;PALASM Design Description
;---------------------------------- Declaration Segment ------------
TITLE Lilith Bank Decoder MMU U2
PATTERN
REVISION 1.0
AUTHOR X. Maas
COMPANY
DATE 05/07/20
CHIP _MMU_U2 PAL22V10
;---------------------------------- PIN Declarations ---------------
PIN 1 PHI2 ;
PIN 2 RW ;
PIN 3 BA16 ;
PIN 4 BA17 ;
PIN 5 BA18 ;
PIN 6 BA19 ;
PIN 7 BA20 ;
PIN 8 BA21 ;
PIN 9 BA22 ;
PIN 10 BA23 ;
PIN 11 VPA ;
PIN 13 VDA ;
PIN 14 ADDR_VALID ;-- Active Low
PIN 20 ROM_HIGH ;-- Active Low
PIN 21 OE ;-- Active Low
PIN 22 WE ;-- Active Low
PIN 23 BANK00 ;-- Active Low
;----------------------------------- Boolean Equation Segment ------
EQUATIONS
ADDR_VALID = /(VPA + VDA);
WE = /(PHI2 * /RW);
OE = /(PHI2 * RW);
BANK00 = /(/BA16 * /BA17 * /BA18 * /BA19 * /BA20 * /BA21 * /BA22 * /BA23);
; BA16 is used for extra 64kByte RAM
; Currently we are not using banks BA18+
ROM_HIGH = /(BA17 + BA18 + BA19 + BA20 + BA21 + BA22 + BA23);
;-------------------------------------------------------------------